Basic Timing - Hitachi SH7095 Hardware User Manual

7.6.3

Basic Timing

The basic timing of the DRAM access is 3 cycles. Figure 7.31 shows the basic DRAM access
timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle and Tc2
is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access
overlaps the Tc2 cycle of the previous access, so accesses can be performed at a minimum of 3
cycles each.
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