Dram Interface; Dram Direct Connection - Hitachi SH7095 Hardware User Manual

c. No PLL Used
7.6

DRAM Interface

7.6.1

DRAM Direct Connection

When the DRAM and other memory enable bits (DRAM2–DRAM0) of BCR1 are set to 010, CS3
space becomes DRAM space, and a DRAM interface function can be used to directly connect the
SH7095 to the DRAM.
The data width of an interface can be 16 or 32 bits (figures 7.29 and 7.30). Two-CAS 16-bit
DRAMs can be connected, since CAS is used to control byte access. The RAS, CASHH, CASHL,
CASLH, CASLL, and RD/WR signals are used to connect the DRAM. When the data width is 16
bits, CASHH, and CASHL are not used. In addition to ordinary read and write access, burst access
using high-speed page mode is also supported.
168 Hitachi
Figure 7.28 Phase Shift With the PLL (cont)