Description Of Registers; Bus Control Register 1 (Bcr1) - Hitachi SH7095 Hardware User Manual

7.2

Description of Registers

7.2.1

Bus Control Register 1 (BCR1)

Bit:
Bit name: MASTER
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Initialize ENDIAN, BSTROM, PSHR and DRAM2–DRAM0 bits after a power-on reset and do
not write to them thereafter. To change other bits by writing to them, write the same bit they are
initialized to. Do not access any space other than CS0 until the register initialization ends.
• Bit 15—Bus Arbitration (MASTER): The MASTER bit is used to check the settings of the
bus arbitration function set by the mode settings with the external input pin. It is a read-only
bit.
Bit 15 (MASTER)
0
1
• Bits 14, 13, and 3—Reserved bits: These bits always read 0.
• Bit 12—Endian Specification of Area 2 (ENDIAN): For big Endian, the MSB of byte data is
the lowest byte address and byte data goes in order toward the LSB. For little Endian, the LSB
of byte data is the lowest byte address and byte data goes in order toward the MSB. When this
bit is 1, the data is rearranged into little Endian before transfer when the CS2 space is read or
written to. It is used when handling data with little Endian processors or running programs
written with little Endian in mind.
Bit 12 (ENDIAN)
0
1
124 Hitachi
15 14
—
— 0
R R
7 6
A1LW1 A1LW0 A0LW1
1 1
R/W R/W
Description
Master mode
Slave mode
Description
Big Endian, as in other areas (Initial value)
Little Endian
13 12
— ENDIAN BSTROM PSHR
0 0
R R/W
5 4
A0LW0
1 1
R/W R/W
11 10
AHLW1 AHLW0
0 0
R/W R/W R/W
3 2
— DRAM2 DRAM1 DRAM0
0 0
R R/W R/W
9 8
1 1
R/W
1 0
0 0
R/W