Hitachi SH7095 Hardware User Manual page 96

3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3–I0) in the CPU's status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is held pending. If the request priority
level is higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and
sends an interrupt request signal to the CPU.
4. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
next instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing.
5. SR and PC are saved onto the stack.
6. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0)
in the status register (SR).
7. When external vector mode is specified for the IRL interrupt, the vector number is read from
the external vector number input pins (D7–D0).
8. The CPU reads the start address of the exception service routine from the exception vector
table for the accepted interrupt, jumps to that address, and starts executing the program there.
This jump is not a delay branch.
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