Hitachi SH7095 Hardware User Manual page 13

On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) and
•
multiplication/accumulation operations (32 bits × 32 bits + 64 bits → 64 bits) executed in 2 to
4 cycles
• Five-stage pipeline
Operating Modes:
• Clock mode: selected from the combination of an on-chip oscillator module, a frequency
doubler circuit, clock output, PLL synchronization, and 90° phase shifting
• Slave/master mode
• Processing states
— Power-on reset state
— Manual reset state
— Exception processing state
— Program execution state
— Power-down state
— Bus-released state
• Power-down states
— Sleep mode
— Standby mode
— Module stop mode
Interrupt:
• Five external interrupt pins (NMI, IRL0 to IRL3) and IRL0 to IRL3 pins set 15 controller
(INTC) external interrupt levels
Eleven internal interrupt sources (DMAC × 2, DIVU × 1, FRT × 3, WDT × 1, SCI × 4,
•
REF × 1)
• Sixteen programmable priority levels
• Vector numbers settable in every internal interrupt source
• Auto-vector or external vector selectable as external interrupt vector by IRL0 to IRL3 pins
User Break:
• Generates an interrupt when the CPU or DMAC generates an address, data, and controller
(UBC) a bus cycle with specified conditions (address, data, CPU/peripheral cycle, instruction
fetch/data access, read/write, byte/word/longword access)
• Simplifies configuration of a self-debugger
Clock/Phase Locked Loop (PLL):
• Built-in clock pulse generator
2 Hitachi