Single Read - Hitachi SH7095 Hardware User Manual

Figure 7.16 Burst Read Wait Specification Timing (Auto Precharge)
7.5.4

Single Read

When a cache area is accessed and there is a cache miss, the cache fill cycle is performed in 16-
byte units. This means that all the data read in the burst read is valid. Since the required data when
a cache-through area is accessed is the maximum length is 32 bits, however, the remaining 12
bytes are wasted. The same kind of wasted data access is produced when synchronous DRAM is
specified as the source in a DMA transfer by DMAC and the transfer unit is something other than
16 bytes. Figure 7.17 shows the timing of a single address read. Because the synchronous DRAM
is set to the burst read/single write mode, the read data output continues after the required data is
received. To avoid data conflict, an empty read cycle is performed from Td2 to Td4 after the
required data is read in Td1 and the device waits for the end of synchronous DRAM operation. In
this case, data is only fetched in Td1, so the BS signal is asserted for Td1 only.
When the data width is 16 bits, the number of burst transfers during a read is 8. BS is asserted and
data fetched in cache-through and other DMA read cycles in the 8 cycles from Td1 to Td8 only in
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