Section 8 Cache; Introduction - Hitachi SH7095 Hardware User Manual

Section 8 Cache

8.1

Introduction

Figure 8.1 Cache Configuration
The SH7095 incorporates 4-kbyte of 4-way cache memory of an instruction/data combination
type. The SH7095 can also be used as 2-kbyte RAM and 2-kbyte cache memory (instruction/data
combination type) by setting the values of the cache control register CCR (two-way cache mode).
The CCR can specify that either of an instruction or data does not use cache.
Each line of cache memory consists of 16 bytes. Cache memory is always updated in line units.
Four 32-bit accesses are required to update a line. Since the number of entries is 64, the six bits
(A9 to A4) in each address determine the entry. A four-way set associative configuration is used,
so up to four different instructions/data can be stored in the cache even when entry addresses
match. To efficiently use four ways having the same entry address, replacement is provided based
on the pseudo least-recently used (LRU) replacement algorithm.
Hitachi 203