Hitachi SH7095 Hardware User Manual page 393

1. Set the TME bit in the watchdog timer's WTCSR to 0.
2. Set the overflow time in CKS2 to CKS0 bits in the watchdog timer's WTCSR (overflow time
should be calculated using the clock frequency after modification).
3. After the SLEEP instruction is executed and standby mode is entered, apply low level from
the CKPREQ/CKM pin.
4. When the LSI is internally ready to modify the operating clock, low level is output from the
CKPACK pin.
5. After the CKPACK pin becomes low, the clocks are stopped and the frequency is modified.
The LSI is internally equivalent to standby mode.
6. When the clock pause state (standby) is canceled, the WDT starts to count up at the falling
edge or rising edge of the NMI pin (when the NMIE bit of the INTC is set).
7. When a frequency is modified, the CKPACK pin becomes high after the time set by the
WDT, and the clock pause function informs the outside that the LSI can again be operated
(the standby mode is canceled).
8. When a clock is halted, the clock is applied again to the CKIO pin and NMI input is
generated. After the time set by the WDT, the CKPACK pin becomes high, the clock pause
function infroms the outside that the LSI can again be operated (the standby mode is
canceled).
The standby state, all internal functions and all pin states during clock pause are equivalent to
those of the normal standby mode. Figure 14.2 shows the timing chart of the clock pause function.
382 Hitachi
Figure 14.2 Clock Pause Function Timing