Hitachi SH7095 Hardware User Manual page 410

Table 15.6 Bus Timing (Conditions: V
Item
DACK delay time 1
DACK delay time 2
Wait setup time
Wait hold time
RAS delay time 1 (SDRAM)
RAS delay time 2 (DRAM)
CAS delay time 1 (SDRAM)
CAS delay time 2 (DRAM)
DQM delay time
CKE delay time
CE delay time 1
OE delay time 1
IVECF delay time
Address input setup time
Address input hold time
BS input setup time
BS input hold time
Read write input setup time
Read write input hold time
Address hold time 1
= 5.0 V ±10%, Ta = -20 to +75°C) (cont)
CC
Symbol Min
t —
DACD1
t —
DACD2
t 20
WTS
t 5
WTH
t —
RASD1
t 1/2 tcyc + 3 1/2 tcyc + 18
RASD2
t —
CASD1
t 1/2 tcyc + 3 1/2 tcyc + 18
CASD2
t —
DQMD
t —
CKED
t 1/2 tcyc + 3 1/2 tcyc + 18
CED1
t —
OED1
t —
IVD
t 14
ASIN
t 3
AHIN
t 15
BSS
t 3
BSH
t 15
RWS
t 3
RWH
t 5
AH1
Max Unit Figures
18 ns
1/2 tcyc + 18 ns
— ns
— ns
18 ns
ns
18 ns
ns
18 ns
21 ns
ns
1/2 tcyc + 18 ns
18 ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns
15.14, 15.20,
15.40, 15.52,
15.66
15.14, 15.20,
15.40, 15.52,
15.66
15.19, 15.43,
15.55, 15.66,
15.70
15.19, 15.43,
15.55, 15.66,
15.70
15.20
15.40
15.20
15.40
15.20
15.37
15.52
15.52
15.68
15.71
15.71
15.71
15.71
15.71
15.71
15.15
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