Hitachi SH7095 Hardware User Manual page 10

12.4.4 System Reset With WDTOVF................................................................. 321
12.4.5 Internal Reset With the Watchdog Timer................................................... 321
Section 13 Serial Communication Interface
13.1 Overview ....................................................................................................... 323
13.1.1 Features .............................................................................................. 323
13.1.2 Block Diagram..................................................................................... 324
13.1.3 Pin Configuration ................................................................................. 324
13.1.4 Register Configuration........................................................................... 325
13.2 Register Descriptions........................................................................................ 325
13.2.1 Receive Shift Register ........................................................................... 325
13.2.2 Receive Data Register............................................................................ 325
13.2.3 Transmit Shift Register .......................................................................... 326
13.2.4 Transmit Data Register .......................................................................... 326
13.2.5 Serial Mode Register ............................................................................. 326
13.2.6 Serial Control Register........................................................................... 329
13.2.7 Serial Status Register............................................................................. 332
13.2.8 Bit Rate Register (BRR)......................................................................... 336
13.3 Operation ....................................................................................................... 341
13.3.1 Overview ............................................................................................ 341
13.3.2 Operation in Asynchronous Mode............................................................ 344
13.3.3 Multiprocessor Communication............................................................... 354
13.3.4 Clocked Synchronous Operation.............................................................. 362
13.4 SCI Interrupt Sources and the DMAC.................................................................. 371
13.5 Notes on Use .................................................................................................. 371
Section 14 Power-Down Modes
14.1 Overview ....................................................................................................... 375
14.1.1 Power-Down Modes.............................................................................. 375
14.1.2 Register .............................................................................................. 376
14.2 Description of Register ..................................................................................... 377
14.2.1 Standby Control Register (SBYCR) ......................................................... 377
14.3 Sleep Mode .................................................................................................... 379
14.3.1 Transition to the Sleep Mode .................................................................. 379
14.3.2 Canceling the Sleep Mode ...................................................................... 379
14.4 Standby Mode................................................................................................. 379
14.4.1 Transition to the Standby Mode............................................................... 379
14.4.2 Canceling the Standby Mode................................................................... 380
14.4.3 Standby Mode Cancellation by NMI......................................................... 381
14.4.4 Clock Pause Function ............................................................................ 381
14.4.5 Notes on Standby Mode ......................................................................... 383
14.5 Module Standby Function.................................................................................. 383
14.5.1 Transition to Module Standby Function..................................................... 383
...................................................... 323
........................................................................ 375
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