command can be issued to that bank until the precharge is completed. For that reason, besides a
cycle Tap to wait for the precharge during read accesses, the issuing of any new commands to the
same bank during this period is delayed by adding a cycle Trw1 to wait until the precharge is
started up. The number of cycles in the Trw1 cycle can be specified using the TRWL bit of the
MCR.
Figure 7.18 Basic Write Cycle Timing (Auto Precharge)
Hitachi 153