Register Configuration; Register Descriptions; Receive Shift Register; Receive Data Register - Hitachi SH7095 Hardware User Manual

13.1.4

Register Configuration

Table 13.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 13.2 Registers
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register

Receive data register

Note: The only value that can be written is a 0 to clear the flags.
13.2

Register Descriptions

13.2.1

Receive Shift Register

The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the
RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte
has been received, it is automatically transferred to the RDR. The CPU cannot read or write the
RSR directly.
Bit:
Bit name:
R/W:
13.2.2 Receive Data Register
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a reset or in standby
or module standby modes.
Abbreviation R/W
SMR
BRR
SCR
TDR
SSR
RDR
7 6
— — —
Initial Value Address
R/W H'00
R/W H'FF
R/W H'00
R/W H'FF
*
R/(W) H'84
R H'00
5 4 3
— —
Access size
H'FFFFFE00 8
H'FFFFFE01 8
H'FFFFFE02 8
H'FFFFFE03 8
H'FFFFFE04 8
H'FFFFFE05 8
2 1
— —
Hitachi 325
0
—