Hitachi SH7095 Hardware User Manual page 527

BSC
Bit Bit Name
15 RAS precharge time
(TRP)
14 RAS-CAS delay (RCD)
13 Wrirte-precharge delay
(TRWL)
12, 11 CAS-before-RAS
refresh RAS assert time
(TRAS1-TRAS0)
10 Burst enable (BE)
9 Bank active mode
(RASD)
516 Hitachi
Value
1 cycle (initial value)
0
2 cycles
1
1 cycle (initial value)
0
2 cycles
1
1 cycle (initial value)
0
2 cycles
1
0 2 cycles (initial value)
0
1 3 cycles
0
0 4 cycles
1
1 Reserved (do not set)
1
0 Burst disabled (initial value)
1 High-sped page mode during DRAM interface is
enabled. Data is continuously transferred in static
column mode during pseudo SRAM interface. During
synchronous DRAM access, burst is always enabled
regardless of this bit.
0 For synchronous DRAM, read or write is performed
using auto-precharge mode.
The next access always starts with bank active
commands.
1 Far synchronous DRAM, access ends with bank active
status. This is only valid for area 3. When area 2 is
synchronous DRAM, the mode is always auto
precharge.
Description