Section 4 Exception Processing; Overview; Types Of Exception Processing And Priority Order - Hitachi SH7095 Hardware User Manual

4.1

Overview

4.1.1

Types of Exception Processing and Priority Order

Exception processing is initiated by four sources: resets, address errors, interrupts, and instructions
(table 4.1). When several exception processing sources occur at once, they are processed
according to priority.
Table 4.1 Types of Exception Processing and Priority Order
Exception Source
Reset Power-on reset
Manual reset
Address CPU address error
error
DMA address error
Interrupt NMI
User break
IRL (IRL1–IRL15 (set with IRL3, IRL2, IRL1, IRL0 pins))
On-chip peripheral modules
Instructions Trap instruction (TRAPA)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly following a delay
branch instruction
Notes: 1. Delay branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.

Section 4 Exception Processing

*1
or instructions that rewrite the PC
Division unit (DIVU)
Direct memory access controller (DMAC)
Watchdog timer (WDT)
Compare match interrupt (part of the bus
state controller)
Serial communications interface (SCI)
16-bit free-running timer (FRT)
*2
)
Priority
High
Low
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