Hitachi SH7095 Hardware User Manual page 44

Table 2.13 Arithmetic Instructions
Instruction
ADD Rm,Rn
ADD #imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ
Rn
CMP/PL
Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010001
0100nnnn00010101
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
If Rn = Rm, 1 → T
If Rn≥Rm with
unsigned data, 1 → T
If Rn ≥ Rm with
signed data, 1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with
signed data, 1 → T
If Rn ≥ 0, 1 → T
If Rn > 0, 1 → T
If Rn and Rm have
an equivalent byte,
1 → T
Single-step division
(Rn/Rm)
MSB of Rn → Q,
MSB of Rm → M,
M ^ Q → T
0 → M/Q/T
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64
bit
Executio
n Cycles T Bit
1 —
1 —
1 Carry
1 Overflow
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Comparison
result
1 Calculation
result
1 Calculation
result
1 0
*
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