Hitachi SH7095 Hardware User Manual page 275

Transfer Width: Byte, word, longword
Transfer bus mode: Cycle steal mode
Transfer address modes: Dual and single modes
DREQ detection method: Level detection
DACK output timing: Read (dual), DMAC cycle (single)
Bus cycle: Basic bus cycle
Notes: 1. Request detection
2. Request detection not established.
Figure 9.39 Timing of DREQ Pin Input Detection in Cycle Steal Mode
• Cycle Steal Mode Level Detection
Requests can be detected for the first time 3 cycles after the bus cycle prior to the DMAC read
cycle and detection starts sometime between then and 2 cycles after DACK output (figure
9.40, 41). This varies with the fluctuations of waits and the like. This means that if request
output is stopped within 3 cycles from the bus cycle prior to the DMAC read cycle, the next
DMA transfer is not performed; if request output is stopped within 2 cycles of DACK output,
the next DMA transfer may sometimes be performed. See Examples of Handling of Request
Signal Acceptance later in this section (9.3.7).
264 Hitachi
with Level Detection (1)