Free-Running Timer Control/Status Register (Ftcsr) - Hitachi SH7095 Hardware User Manual

• Bits 6 to 4: Reserved. These bits always read 0. The write value should always be 0. Do not
write 1.
• Bit 3: Output compare interrupt A enable (OCIAE). Selects enable/disable for interrupt
requests from the OCFA (OCIA) when the output compare flag A (OCFA) of the FTCSR is
set to 1.
Bit 3 (OCIAE)
0
1
• Bit 2: Output compare interrupt B enable (OCIBE). Selects enable/disable for interrupt
requests from the OCFB (OCIB) when the output compare flag B (OCFB) of the FTCSR is
set to 1.
Bit 2 (OCIBE)
0
1
• Bit 1: Timer overflow interrupt enable (OVIE). Selects enable/disable for interrupt requests
from the OVF (OVI) when the overflow flag (OVF) of the FTCSR is set to 1.
Bit 1 (OVIE)
0
1
• Bit 0: Reserved. This bit always reads 1. The write value should always be 1.
11.2.5

Free-Running Timer Control/Status Register (FTCSR)

Bit:
Bit name:
Initial value:
R/W:
Note: For bits 7, and 3 to 1, the only value that can be written is 0 (for clearing the flags).
290 Hitachi
Description
Disables interrupt requests (OCIA) from the OCFA (initial value)
Enables interrupt requests (OCIA) from the OCFA
Description
Disables interrupt requests (OCIB) from the OCFB (initial value)
Enables interrupt requests (OCIB) from the OCFB
Description
Disables interrupt requests (FOVI) from the OVF (initial value)
Enables interrupt requests (FOVI) from the OVF
7 6
ICF —
0 0
R/(W)* —
5 4
— — OCFA
0 0
— — R/(W)*
3 2
OCFB OVF
0 0
R/(W)* R/(W)*
1 0
CCLRA
0 0
R/W