Hitachi SH7095 Hardware User Manual page 102

3. Clearing Sources:
Interrupts Sources: When an interrupt source is cleared by the program, the operation of
pipelines must be taken into account to ensure that the same interrupt does not occur again.
External Interrupt Sources: When an interrupt source is cleared by writing to an I/O address,
another instruction will be executed before the write can be completed because of the write
buffer. To ensure that the next instruction is executed after the write is complete, read from
the same address after the write to obtain total synchronization.
• Returning from interrupt processing with an RTE instruction: Figure 5.11 shows how a
minimum interval of 1 cycle is required between the read instruction used for
synchronization and the RTE instruction. A read instruction for synchronization and a
minimum of 1 instruction should thus be executed between the source clear and the RTE
instruction.
• Changing the level during interrupt processing: Figure 5.12 shows how a minimum
interval of 4 cycles is required between the synchronization instruction and the LDC
instruction when an LDC instruction is used to enable another overlapping interrupt by
changing the SR value. A read instruction for synchronization and a minimum of 4
instructions should thus be executed between the source clear and the LDC instruction.
Figure 5.10 Clearing NMI Request
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