Dma Vector Number Registers 0 And 1 (Vcrdma0, Vcrdma1) - Hitachi SH7095 Hardware User Manual

Bit 1: TE
0
1
• Bit 0—DMA Enable Bit (DE): Enables or disables DMA transfers. In the auto-request mode,
the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The NMIF and AE
bits of the DMAOR and the TE bit must be all set to 0. In external request mode or on-chip
peripheral module request mode, the transfer begins when the DMA transfer request is
received from said device or on-chip peripheral module, provided this bit and the DME bit are
set to 1. As with the auto-request mode, the TE bit and the NMIF and AE bits of the DMAOR
must be all set to 0. The transfer can be stopped by clearing this bit to 0. The DE bit is
initialized to 0 by reset and in the standby mode. Values are held during a module standby.
Bit 0: DE
0
1
9.2.5

DMA Vector Number Registers 0 and 1 (VCRDMA0, VCRDMA1)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
The DMA vector number registers 0 and 1 (VCRDMA0, VCRDMA1) are 32-bit read/write
registers that set the DMAC transfer-end interrupt vector number. Only the lower eight bits of the
32 are effective. They are written as 32-bit values, including the top 24 bits. Write the initial
values to the top 24 bits. These bits are initialized to H'000000XX (last eight bits are undefined)
by a reset and in the standby mode. Values are held during a module standby.
• Bits 31–8—Reserved bits: Only write 0 to these bits. They always read 0.
Description
DMA has not ended or was aborted (Initial value)
Cleared by reading 1 from the TE bit and then writing 0.
DMA has ended normally (by TCR = 0)
Description
DMA transfer disabled (Initial value)
DMA transfer enabled
31 30
— —
0 0
R R
7 6
VC7 VC6 VC5
— —
R/W R/W R/W
29 ... 11
— ... —
0 ...
R ...
5 4
VC4 VC3
— — —
R/W R/W
10
— —
0 0
R R
3 2
VC2 VC1
— —
R/W R/W
9 8
—
0 0
R R
1 0
VC0
—
R/W
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