Hitachi SH7095 Hardware User Manual page 498

Timer control register (TCR)
Item 7
Bit name IEDGA
Initial Value 0
R/W R/W
Bit Bit Name
7 Input edge select
(IEDG)
1, 0 Clock selects
(CKS1 and CKS0)
Timer output compare control
register (TOCR)
Item 7
Bit name –
Initial Value 1
R/W –
Bit Bit Name
4 Output compare register
select (OCRS)
1 Output level A (OLVLA)
0 Output level B (OLVLB)
H'FFFFFE16
6 5
– –
0 0
R/W R/W
Value
0 Iaptures input on falling edge (initial value)
1 Captures input on rising edge
0 0 nternal clock: count at φ/8 (initial value)
0 1 Internal clock: count at φ//32
1 0 Internal clock: count at φ//128
1 1 External clock: count at rising edge
H'FFFFFE17
6 5
– –
1 1
– –
Value
0 Selects OCRA register
1 Selects OCRB register
0 Outputs 0 on compare match A
1 Outputs 1 on compare match A
0 Outputs 0 on compare match B
1 Outputs 1 on compare match B
8
Bit
4 3
– –
0 0
R/W R/W
Description
8
Bit
4 3
OCRS –
0 0
R/W R/W
Description
2 1
– CKS1
0 0
R/W R/W
2 1
– OLVLA
0 0
R/W R/W
(initial value)
(initial value)
(initial value)
Hitachi 487
0
CKS0
0
R/W
0
OLVLB
0
R/W