Hitachi SH7095 Hardware User Manual page 89

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
• Bits 15 to 12—Serial communication interface (SCI) interrupt priority level (SCIIP3–
SCIIP0): These bits set the serial communications interface (SCI) interrupt priority level.
There are four bits, so levels 0–15 can be set.
• Bits 11 to 8—Free-running timer (FRT) interrupt priority level (FRTIP3–FRTIP0): These bits
set the free-running timer (FRT) interrupt priority level. There are four bits, so levels 0–15
can be set.
• Bits 7 to 0—Reserved bits: These bits always read 0. The write value should always be 0.
Table 5.5 shows the relationship between on-chip peripheral module interrupts and interrupt
priority level setting registers.
Table 5.5 Interrupt Request Sources and IPRA/IPRB
Register Bits 15 to 12
IPRA DIVU
IPRB SCI
As table 5.5 shows, two or three on-chip peripheral modules are assigned to each interrupt priority
register. Set the priority levels by setting the corresponding 4-bit groups (bits 15 to 12, bits 11 to 8
and bits 7 to 4) with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level
0 (the lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to
the same bits (DMAC0 and DMAC1, or WDT and DRAM refresh control unit), those two
modules have the same priority. A reset initializes IPRA and IPRB to H'0000. They are not
initialized by the standby mode.
78 Hitachi
15 14
SCIIP3 SCIIP2 SCIIP1
0 0
R/W R/W
7 6
— —
0 0
R R
Bits 11 to 8
DMAC0, DMAC1
FRT
13 12
SCIIP0 FRTIP3 FRTIP2 FRTIP1 FRTIP0
0 0
R/W R/W R/W
5 4
— —
0 0
R R
Bits 7 to 4
WDT
Reserved
11 10
0 0
R/W R/W
3 2
— —
0 0
R R
Bits 3 to 0
Reserved
Reserved
9 8
0 0
R/W
1 0
— —
0 0
R R