Pin Configuration - Hitachi SH7095 Hardware User Manual

7.1.3

Pin Configuration

Table 7.1 lists the bus state controller pin configuration.
Table 7.1 Pin Configuration
With Bus
Signal I/O Released
A26–A0 I/O I
D31–D0 I/O Hi-Z
BS I/O I
CS0–CS3 O Hi-Z
RD/WR, I/O I
WE
O Hi-Z
RAS, CE
O Hi-Z
CAS, OE
O Hi-Z
CASHH,
DQMUU,
WE3
O Hi-Z
CASHL,
DQMUL,
WE2
120 Hitachi
Description
Address bus. 27 bits are available to specify a total 128 Mbytes of
memory space. The most significant 2 bits are used to specify the
CS space, so the size of the spaces are 32 Mbytes. When the bus
is released, these become inputs for the external bus cycle
address monitor.
32-bit data bus. When reading or writing a 16-bit width area, use
D15–D0; when reading or writing a 8-bit width area, use D7–D0.
With 8-bit accesses that read or write a 32-bit width area, input and
output the data via the byte position determined by the lower
address bits of the 32-bit bus.
Indicates start of bus cycle or monitor. With the basic interface
(device interfaces except for DRAM, synchronous DRAM, pseudo
SRAM), signal is asserted for a single clock cycle simultaneous
with address output. The start of the bus cycle can be determined
by this signal. This signal is asserted for 1 cycle synchronous with
column address output in DRAM, synchronous DRAM and pseudo
SRAM accesses. When the bus is released, the BS becomes an
input for address monitoring of external bus cycles.
Chip select. Signal that selects area; specified by A26 and A25.
Read/write signal. Signal that indicates access cycle direction
(read/write). Connected to WE pin when a DRAM/synchronous
DRAM is connected. When the bus is released, becomes an input
for address monitoring of external bus cycles.
RAS pin for DRAM/synchronous DRAM. CE pin for pseudo SRAM.
Open when using DRAM. CAS pin for synchronous DRAM. OE pin
for pseudo SRAM.
When DRAM is used, connected to CAS pin for the most significant
byte (D31–D24). When synchronous DRAM is used, connected to
DQM pin for the most significant byte. When pseudo SRAM is
used, connected to WE pin for the most significant byte. For basic
interface, indicates writing to the most significant byte.
When DRAM is used, connected to CAS pin for the second byte
(D23–D16). When synchronous DRAM is used, connected to DQM
pin for the second byte. When pseudo SRAM is used, connected to
WE pin for the second byte. For basic interface, indicates writing to
the second byte.