Hitachi SH7095 Hardware User Manual page 504

Vector number setting register
DMA0 and DMA1 (VCRDMA0,
VCRDMA1)
Item 31 30
Bit name – –
Initial Value 0 0
R/W R R
Item 15 14
Bit name – –
Initial Value 0 0
R/W R R
Bit
7 to 0 Vector number bits (VC7-VC0)
VInterrupt control register (ICR)
Item 15 14
Bit name
NMIL –
Initial Value 0/1* 0
R/W R R
Note: When NMI input is high: 1; when NMI input is low: 0
Bit Bit Name
15 NMI input level (NMIL)
8 NMI edge select (NMIE)
1 RL interrupt vector
mode select (VECMD)
H'FFFFFFA0 (channel 0)
H'FFFFFFA8 (channel 1)
29 28 27 26
– – – –
0 0 0 0
R R R R
13 12 11 10
– – – –
0 0 0 0
R R R R
Bit nam
H'FFFFFEE0
13 12 11 10
– – – –
0 0 0 0
R R R R
Value
0 NMI input level is low
1 NMI input level is high
0 Interrupt request is detected on falling edge of NMI input
1 Interrupt request is detected on rising edge of NMI input
0 Auto vector mode, set internally
1 External vector mode, external input
Bit
25 24 23 22
– – – –
0 0 0 0
R R R R
9 8 7 6
– – VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0
0 0 – –
R R R/W R/W R/W R/W R/W R/W R/W R/W
These bits set the vector number at the end of the
DMAC transfer.
8/16
Bit
9 8 7 6
– NMIE – –
0 0 – –
R R/W R R
Description
INTC
32
21 20 19 18
– – – –
0 0 0 0
R R R R
5 4 3 2
– – – –
Description
5 4 3 2
– – – –
– – – –
R R R R
(initial value)
(initial valne)
17 16
– –
0 0
R R
1 0
– –
1 0
VEC
– MC
– –
R R/W
Hitachi 493