Address Multiplex - Hitachi SH7095 Hardware User Manual

Figure 7.14 Synchronous DRAM 16-bit Device Connection
7.5.2

Address Multiplex

Addresses are multiplexed according to the MCR's address multiplex specification bits AMX2–
AMX0 and size specification bit SZ so that synchronous DRAMs can be connected directly
without an external multiplex circuit. Table 7.4 lists the relationship between the multiplex
specification bit and bit output to the address pin.
A26–A14 and A0 always output the original value regardless of multiplexing.
When SZ = 0, the data width on the synchronous DRAM side is 16 bits and the LSB of the
device's address pins (A0) specifies word address. The A0 of the synchronous DRAM is thus
connected to the A1 pin of the SH7095, the rest of the connection proceeding in the same order,
beginning with the A1 pin to the A2 pin.
When SZ = 1, the data width on the synchronous DRAM side is 32 bits and the LSB of the
device's address pins (A0) specifies longword address. The A0 of the synchronous DRAM is thus
connected to the A2 pin of the SH7095, the rest of the connection proceeding in the same order,
beginning with the A1 pin to the A3 pin.
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