Table Of Contents - Hitachi SH7095 Hardware User Manual

Section 1 Overview and Pin Functions
1.1 SH7095 Features.............................................................................................
1.1.1 Features of the SH7095 .........................................................................
1.2 Block Diagram................................................................................................
1.3 Description of Pins ..........................................................................................
1.3.1 Pin Arrangement ..................................................................................
1.3.2 Pin Functions.......................................................................................
Section 2 CPU
...................................................................................................
2.1 Register Configuration .....................................................................................
2.1.1 General Registers .................................................................................
2.1.2 Control Registers.................................................................................. 14
2.1.3 System Registers..................................................................................
2.1.4 Initial Values of Registers ......................................................................
2.2 Data Formats..................................................................................................
2.2.1 Data Format in Registers........................................................................ 16
2.2.2 Data Format in Memory ........................................................................
2.2.3 Immediate Data Format .........................................................................
2.3 Instruction Features .........................................................................................
2.3.1 RISC-Type Instruction Set .....................................................................
2.3.2 Addressing Modes................................................................................
2.3.3 Instruction Format ................................................................................
2.4 Instruction Set ................................................................................................
2.4.1 Instruction Set by Classification ..............................................................
2.4.2 Operation Code Map.............................................................................
2.5 Processing States.............................................................................................
2.5.1 State Transitions................................................................................... 42
2.5.2 Power-Down State................................................................................
Section 3 Operating Mode
3.1 Operating Mode of the On-chip Clock Pulse Generator...........................................
3.1.1 Clock Pulse Generator...........................................................................
3.1.2 Clock Operating Mode ..........................................................................
3.2 Bus Width of the CS0 Area ...............................................................................
3.3 Switching between Master and Slave Modes.........................................................
3.4 Cache Control Register.....................................................................................
Section 4 Exception Processing
4.1 Overview.......................................................................................................
Page ii
Contents
.............................................................
.................................................................................
........................................................................
1
1
1
5
6
6
7
13
13
13
14
15
16
16
17
17
17
20
23
27
27
40
42
44
47
47
47
49
50
51
51
53
53