Hitachi SH7095 Hardware User Manual page 412

Table 15.7 Bus Timing With PLL On and 1/4 Cycle Delay (Conditions: V
Ta = -20 to +75°C) (cont)
Item
DACK delay time 1
DACK delay time 2
Wait setup time
Wait hold time
RAS delay time 1 (SDRAM) t
RAS delay time 2 (DRAM)
CAS delay time 1 (SDRAM) t
CAS delay time 2 (DRAM)
DQM delay time
CKE delay time
CE delay time 1
OE delay time 1
IVECF delay time
Address input setup time
Address input hold time
BS input setup time
BS input hold time
Read write input setup time t
Read write input hold time
Address hold time 1
Symbol Min
t —
DACD1
t —
DACD2
t 20 – 1/4 tcyc —
WTS
t 1/4 tcyc + 5 —
WTH
—
RASD1
t 3/4 tcyc + 3 3/4 tcyc + 18
RASD2
—
CASD1
t 3/4 tcyc + 3 3/4 tcyc + 18
CASD2
t —
DQMD
t —
CKED
t 3/4 tcyc + 3 3/4 tcyc + 18
CED1
t —
OED1
t —
IVD
t 14 - 1/4 tcyc —
ASIN
t 1/4 tcyc + 3 —
AHIN
t 15 - 1/4 tcyc —
BSS
t 1/4 tcyc + 3 —
BSH
15 - 1/4 tcyc —
RWS
t 1/4 tcyc + 3 —
RWH
t 5
AH1
Max Unit Figures
1/4 tcyc + 18 ns
3/4 tcyc + 18 ns
ns
ns
1/4 tcyc + 18 ns
ns
1/4 tcyc + 18 ns
ns
1/4 tcyc + 18 ns
1/4 tcyc + 21 ns
ns
3/4 tcyc + 18 ns
1/4 tcyc + 18 ns
ns
ns
ns
ns
ns
ns
— ns
= 5.0 V ±10%,
CC
15.14, 15.20, 15.40,
15.52, 15.66
15.14, 15.20, 15.40,
15.52, 15.66
15.19, 15.43, 15.55,
15.66, 15.70
15.19, 15.43, 15.55,
15.66, 15.70
15.20
15.40
15.20
15.40
15.20
15.37
15.52
15.52
15.68
15.71
15.71
15.71
15.71
15.71
15.71
15.15
Hitachi 401