Hitachi SH7095 Hardware User Manual page 249

Table 9.4 Selecting External Request Modes with the TA and AM Bits
CHCR
Transfer
TA AM Address Mode
0 0 Dual address
mode
1 Dual address
mode
1 0 Single address
mode
1 Single address
mode
Notes: 1. External memory, memory-mapped external device, on-chip peripheral module
(excluding DMAC, BSC, and UBC).
2. Except synchronous DRAM.
Choose to detect DREQ either by the falling edge or by the level using the DS and DL bits of
CHCR0 and CHCR1 (DS = 0 is level detection, DS = 1 is edge detection; for edge detection,
DL = 0 is rising edge, DL = 1 is falling edge; for level detection, DL = 0 is active low, DL = 1 is
active high). The source of the transfer request does not have to be the data transfer source or
destination.
Table 9.5 Selecting the External Request Signal with the DS and DL Bits
DRCR
DS DL External Request
0 0 Level (active low)
1 Level (active high)
1 0 Edge (falling)
1 Edge (rising)
On-Chip Module Request: In this mode, transfers are started by the transfer request signal
(interrupt request signal) of an on-chip peripheral module on this LSI. The transfer request signals
are the receive-data-full interrupt (RXI) of the serial communication interface (SCI) and the
transmit-data-empty interrupt (TXI) of the SCI (table 9.6). If the DMA transfer is enabled (DE =
1, DME = 1, TE = 0, NMIF = 0, AE = 0), the DMA transfer starts upon the input of a transfer
request signal.
238 Hitachi
Acknowledge Mode
DACK output in read
cycle
DACK output in write
cycle
Data transferred from
memory to device
Data transferred from
device to memory
Source
1
Any*
1
Any*
*2
External memory
or memory-mapped
external device
External device with
DACK
Destination
1
Any*
1
Any*
External device
with DACK
*2
External memory
or memory-mapped
external device