Hitachi SH7095 Hardware User Manual page 194

CE precharge time inserts a Tpw according to the TRP bit of the MCR to extend it to 2 cycles. The
number of cycles between BS assert and the end of access can be extended from 2 to 4 cycles by
setting the W31/W30 bits of the WCR. When anything other than 00 is set in W31 and W30, the
external wait pin WAIT is also sampled, so the number of cycles can be made even longer. Figure
7.40 shows the timing of wait state control using the WAIT pin. In either case, when consecutive
accesses occur, the Tp of one access overlaps with the Tc2 of the previous access. The RCD bit of
the MCR is set to 0 for a pseudo-SRAM interface, but when set to 1, the number of cycles from
the CE assert to the BS assert or write data output becomes 2.
Figure 7.39 Wait State Timing
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