Cache Operation; Cache Reads - Hitachi SH7095 Hardware User Manual

Table 8.2 Address Space and Cache Operation
Addresses
A31–A29 Partial Space
000 Cache area
001 Cache-through area
010 Associative purge area
011 Address array read/write area Cache address array is accessed directly.
110 Data array read/write area
111 I/O area
8.4

Cache Operation

8.4.1

Cache Reads

This section describes cache operation when the cache is enabled and data is read from the CPU.
One of the 64 entries is selected by the entry address part of the address output from the CPU on
the cache address bus. The tag addresses of ways 0 through 3 are compared to the tag address parts
of the addresses output from the CPU. A match to the tag address of a way is called a cache hit. In
proper use, the tag addresses of each way differ from each other, but and the tag address of only
one way will match. When none of the way tag addresses match, it is called a cache miss. Tag
addresses of entries with valid bits of 0 will not match in any case.
When a cache hit occurs, data is read from the data array of the way that was matched according to
the entry address, the byte address within the line, and the access data size. The data is then sent to
the CPU. The address output on the cache address bus is calculated in the CPU's instruction
execution phase and the results of the read are written during the CPU's write back stage. The
cache address bus and cache data bus both operate as pipelines in concert with the CPU's pipeline
structure. From address comparison to data read requires 1 cycle; since the address and data
operate as a pipeline, consecutive reads can be performed at each cycle with no waits.
206 Hitachi
Cache Operation
Cache is used when the CE bit of the CCR is 1.
No cache is used.
Cache line of the specified address is purged
(disabled).
Cache data array is accessed directly.
No cache is used.