Cache Initialization; Associative Purges - Hitachi SH7095 Hardware User Manual

Table 8.3 LRU Information after Update
Bit 5
Way 0 0
Way 1 1
Way 2 —
Way 3 —
—: Holds the value before update.
Table 8.4 Selection Conditions of Replaced Way
Bit 5
Way 0 1
Way 1 0
Way 2 —
Way 3 —
—: Don't care.
8.4.6

Cache Initialization

Purges of the entire cache area can only be done by writing 0 to the CP bit of the CCR. Writing 1
to the CP bit initializes the valid bit of the address array and al bits of the LRU information to 0.
Cache purges are completed in 1 cycle, but additional time is required for writing to the CCR.
Always initialize the valid bit and LRU before enabling the cache.
When the cache is enabled, instruction reads are performed from the cache even during writing to
the CCR. This means that the prefetched instructions are read from the cache. To do a proper
purge, write 0 to the CCR's CE bit, then disable the cache and purge. Since the CCR's CE bit is
cleared to 0 by a power-on reset or manual reset, the cache can be purged immediately by a reset.
8.4.7

Associative Purges

Associative purges invalidate 1 line (16 bytes) corresponding to specific address contents when
the contents are in the cache. When the contents of shared addresses are rewritten by one CPU in a
multiprocessor configuration, the other CPU cache must be invalidated if it also contains the
address. When writing or reading is performed to the address found by adding H'40000000 to the
purged address, the valid bit of the entry storing the address prior to the addition is initialized to 0.
16 bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be
accomplished in 16 writes. Access sizes when associative purges are performed should be
longword. A purge of 1 line requires 2 cycles.
Bit 4 Bit 3
0 0
— —
1 —
— 1
Bit 4 Bit 3
1 1
— —
0 —
— 0
Bit 2 Bit 1
— —
0 0
1 —
— 1
Bit 2 Bit 1
— —
1 1
0 —
— 0
Bit 0
—
—
0
1
Bit 0
—
—
1
0
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