Hitachi SH7095 Hardware User Manual page 346

Bit 2: TEND Description
0 Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writing 0 in TDRE, or the DMAC writes data in TDR.
1 End of transmission (initial value).
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to
0 in the serial control register (SCR), or TDRE is 1 when the last bit of a one-byte
serial character is transmitted.
• Bit 1: Multiprocessor bit (MPB). Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is
a read-only bit and cannot be written.
Bit 1: MPB Description
0 Multiprocessor bit value in receive data is 0 (initial value). If RE is cleared to 0
when a multiprocessor format is selected, the MPB retains its previous value.
1 Multiprocessor bit value in receive data is 1.
• Bit 0: Multiprocessor bit transfer (MPBT). Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous
mode. The MPBT setting is ignored in the clocked synchronous mode, when a multiprocessor
format is not selected, or when the SCI is not transmitting.
Bit 0: MPBT Description
0 Multiprocessor bit value in transmit data is 0 (initial value).
1 Multiprocessor bit value in transmit data is 1.
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