Hitachi SH7095 Hardware User Manual page 20

Table 1.1 Pin Functions (cont)
Pin No. Pin Name
62 V
SS
63 A24
64 A25
65 A26
66 DACK0
67 V
CC
68 DACK1
69 V
SS
70 DREQ0
71 DREQ1
72 CS0
73
CS1
74
CS2
75 CS3
76 BS
77 RD/WR
78 V
SS
79 RAS/ CE
80 CAS/ OE
81
CASHH/DQMUU/WE3
82
CASHL/DQMUL/WE2
83
CASLH/DQMLU/WE1
84 V
CC
85
CASLL/DQMLL/WE0
86 V
SS
87
RD
88 CKE
89
WAIT
90 NC
I/O Pin Description
I Ground
I/O Address bus
I/O Address bus
I/O Address bus
O DMAC0 acknowledge
I Power
O DMAC1 acknowledge
I Ground
I DMAC0 request
I DMAC1 request
O Chip select 0
O Chip select 1
O Chip select 2
O Chip select 3
I/O Bus cycle start
I/O Read/write
I Ground
O RAS for DRAM and synchronous DRAM, CE
for pseudo SRAM
O CAS for synchronous DRAM, OE for pseudo
SRAM
O Most significant byte selection signal for
memory
O Second byte selection signal for memory
O Third byte selection signal for memory
I Power
O Least significant byte selection signal for
memory
I Ground
O Read pulse
O Synchronous DRAM clock enable control
I Hardware wait request
— Reserved pin (do not connect anything to it)
Hitachi 9