Channel Priority - Hitachi SH7095 Hardware User Manual

When RXI (transfer request when the SCI's receive data is full) is set as the transfer request,
however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI
(transfer request when the SCI's transmit data is empty) is set as the transfer request, the transfer
destination must be the SCI's transmit data register (TDR).
Table 9.6 Selecting On-Chip Peripheral Module Request Mode with the AR and RS bits
DMA Transfer
Request
AR RS1 RS0 Source
0 0 1 SCI receiver
0 1 0 SCI transmitter TXI (SCI transmit-data-
Note: External memory, memory-mapped external device, on-chip peripheral module (excluding
DMAC, BSC, and UBC).
When outputting transfer requests from the SCI, its interrupt enable bits (TIE and RIE) must be set
to output the interrupt signals. Note that transfer request signals from on-chip peripheral modules
(interrupt request signals) are sent not just to the DMAC but to the CPU as well. When an on-chip
peripheral module is specified as the transfer request source, set the priority level values in the
interrupt priority level registers (IPRC–IPRE) of the interrupt controller (INTC) at or below the
levels set in the I3–I0 bits of the CPU's status register so that the CPU does not accept the
interrupt request signal.
The DMA transfer request signals of table 9.6 are automatically fetched when the corresponding
DMA transfer is performed. If the cycle-steal mode is being employed, DMA transfer requests
(interrupt request) from any module will be cleared at the first transfer; if the burst mode is being
used, it will be cleared at the last transfer.
9.3.3

Channel Priority

When the DMAC receives simultaneous transfer requests on two channels, it selects a channel
according to a predetermined priority. There are two priority modes, fixed and round-robin. The
channel priority is selected by the priority bit PR in the DMA operation register (DMAOR).
Fixed Priority Mode: In this mode, the priority levels among the channels remain fixed. When
PR is set to 0, the priority, high to low, is channel 0 > channel 1. Figure 9.3 shows an example of a
transfer in burst mode.
DMA Transfer
Request Signal
RXI (SCI receive-data-
full transfer request)
empty transfer request)
Source Destination
RDR0 Any*
Any* TDR0
Bus DREQ
Mode Setting
Cycle- Edge, low
steal active
Cycle- Edge, low
steal active
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