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Table A.1
Pin State During Resets, Power-Down States and Bus Release State (cont)
Category
Direct memory
DACK0, DACK1
access
DREQ0, DREQ1
controller
(DMAC)
16-bit free-
running timer
(FRT)
Serial
communication
interface (SCI)
PLL
I: Input
O: Output
H: High-level output
L: Low-level output
Z: High impedance
K: Input pin is high impedance, output pin holds the state
Notes: 1. Depends on the clock mode. (MD2-MD0 setting).
2. Outputs low in the standby mode when the clock is paused.
3. When the high impedance bit HIZ of the standby control register SBYCR is set to 1, the
output pin becomes high impedance.
Other: During sleep, if the DMAC is running, the address/data bus and bus control signals change
according to the DMAC operation (likewise during refresh).
470 Hitachi
At Power On
Pin
Master Slave Capture Release Standby Sleep Released
FTOA
H
FTOB
FTI
FTCI
RXD
TXD
SCK
CAP2-CAP1
IO
Pin State: Reset
Manual
L
L
L
Z
Z
Z
H
H
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
L
L
Z
Z
Z
IO
IO
Power-Down
3
L
K*
O
Z
Z
I
3
H
K*
O
3
L
K*
O
3
Z
K*
I
3
Z
K*
I
3
Z
K*
I
3
L
K*
O
3
Z
K*
IO
IO
IO
IO
Bus
O
I
O
O
I
I
I
O
I
IO
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