Hitachi SH7095 Hardware User Manual page 59

The pin functions related to the clock pulse generator are shown in table 3.1.
Table 3.1 Pin Functions
Pin Name I/O
CKIO I/O
CAP1 I
CAP2 I
MD0 I
MD1 I
MD2 I
CKPREQ/ I
CKM
O
CKPACK
Note: See section 14.4.4, Clock Pause Function for more information.
PLL Circuit 1: In high-speed operation, the phase difference between reference clocks and
operating clocks in the LSI affects the interface margin with peripheral devices. The on-chip PLL
circuit 1 synchronizes external clocks with clocks provided into the LSI.
The PLL circuit 1 can also make the phase difference between the clocks 90 degrees, enabling
high-speed interface with SDRAM.
48 Hitachi
Function
External clock input pin when PLL circuit 1 is used. Input a frequency
equivalent to the operating frequency.
Connects to capacitance for operating a PLL circuit.
Connects to capacitance for operating a PLL circuit.
The level applied to these pins specifies clock mode.
In modes that only use PLL circuit 1, this pin is used as the clock pause
request pin.
Indicates that a clock pause request has been received.