Hitachi SH7095 Hardware User Manual page 385

Constraints on DMAC Use:
• When using an external clock source for the synchronous clock, update the TDR with the
DMAC, and then after twenty system clocks or more elapse, input a transmit clock. If a
transmit clock is input in the first four system clocks after the TDR is written, an error may
occur (figure 13.22).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source using the resource select bit (RS) in the channel
control register (CHCR).
Note: During external clock operation, an error may occur if t is 4φ or less.
Figure 13.22 Clocked Synchronous Transmitting Example with DMAC
Cautions for Clocked Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCK is 1.
• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed
from 0 to 1.
• When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF is 1 when
RE is set to zero 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it cannot be
copied to RDR.
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