Refreshes - Hitachi SH7095 Hardware User Manual

Figure 7.24 Write Timing (Bank Active, Different Row Addresses)
7.5.7

Refreshes

The bus state controller is equipped with a function to control refreshes of synchronous DRAM.
Auto refreshes can be performed by setting the MCR's RMD bit to 0 and the RFSH bit to 1. When
the synchronous DRAM is not accessed for a long period of time, set the RFSH bit and RMODE
bit both to 1 to start up the self-refresh mode, which uses low consumption power to maintain
data.
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