Hitachi SH7095 Hardware User Manual page 369

Example: 8-bit data with multiprocessor bit and one stop bit
Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.
1. ID receive cycle: set the MPIE bit in the serial control register (SCR) to 1.
2. SCI status check and compare to ID reception: read the serial status register (SSR), check that
RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
3. Receive error handling and break detection: if a receive error occurs (figure 13.12, continued),
read the ORER and FER bits in SSR to identify the error. After executing the necessary error
processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain
set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
4. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data
from the receive data register (RDR).
358 Hitachi
Figure 13.11 SCI Multiprocessor Transmit Operation