Hitachi SH7095 Hardware User Manual page 272

Transfer Width: Byte, word, longword
Transfer bus mode: Cycle steal mode
Transfer address modes: Dual and single modes
DREQ detection method: Edge detection
DACK output timing: Read, write (dual), DMAC cycle (single)
Notes: 1. Request detection
2. When a write (dual) occurs at DACK output, the cycle is a DMAC read. Otherwise,
the cycle is a CPU cycle.
Figure 9.35 DREQ Pin Input Detection Timing in Cycle Steal Mode with Edge Detection (1)
Figures 9.36 and 9.37 show are examples of how to change the bus width of an external
device.
Hitachi 261