Interrupt Priority Level Setting Register B (Iprb) - Hitachi SH7095 Hardware User Manual

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
• Bits 15 to 12—Division unit (DIVU) interrupt priority level (DIVUIP3–DIVUIP0): These bits
set the division unit (DIVU) interrupt priority level. There are four bits, so levels 0–15 can be
set.
• Bits 11 to 8—DMA controller interrupt priority level (DMACIP3–DMACIP0): These bits set
the DMA controller (DMAC) interrupt priority level. There are four bits, so levels 0–15 can
be set. The same level is set for both DMAC channels. When interrupts occur simultaneously,
channel 0 has priority.
• Bits 7 to 4—Watchdog timer (WDT) interrupt priority level (WDTIP3–WDTIP0): These bits
set the watchdog timer (WDT) interrupt priority level and bus state controller (BSC) interrupt
priority level. There are four bits, so levels 0–15 can be set. When WDT and BSC interrupts
occur simultaneously, the WDT interrupt has priority.
• Bits 3 to 0—Reserved bits: These bits always read 0. The write value should always be 0.
5.3.2

Interrupt Priority Level Setting Register B (IPRB)

Interrupt priority level setting register B (IPRB) is a 16-bit read/write register that assigns priority
levels from 0 to 15 to on-chip peripheral module interrupts. IPRB is initialized to H'0000 on reset.
It is not initialized in standby mode.
15 14
DIVU DIVU DIVU
IP3 IP2
0 0
R/W R/W
7 6
WDT WDT
IP3 IP2
0 0
R/W R/W
13 12
DIVU DMAC
IP1 IP0
0 0
R/W R/W
5 4
WDT WDT
IP1 IP0
0 0
R/W R/W
11 10
DMAC DMAC
IP3 IP2
0 0
R/W R/W
3 2
— —
0 0
R R
9 8
DMAC
IP1 IP0
0 0
R/W R/W
1 0
— —
0 0
R R
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