Hitachi SH7095 Hardware User Manual page 79

UBC: User break controller
DMAC: Direct memory access controller
DIVU: Division unit
FRT: Free-running timer
SCI: Serial communications interface
WDT: Watchdog timer
REF: Refresh request within bus state controller
68 Hitachi
ICR:
IPRA/B:
VCRWDT: Vector number setting register WDT
VCRA–D: Vector number setting registers A–D
SR:
Figure 5.1 INTC Block Diagram
Interrupt control register
Interrupt priority level setting
registers A and B
Status register