Hitachi SH7095 Hardware User Manual page 267

Figure 9.26 DACK Output in Synchronous DRAM Write
Figure 9.27 DACK Output in Synchronous DRAM Write
Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory
is set as DRAM and a row address is output during a read or write, the acknowledge signal is
output across the row address and column address (figures 9.28–9.30).
256 Hitachi
(Bank Active, Same Row Address, AM = 1)
(Bank Active, Different Row Address, AM = 1)