Hitachi SH7095 Hardware User Manual page 278

Transfer Width: 16-byte
Transfer bus mode: Cycle steal mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write cycle
Bus cycle: Basic bus cycle
Notes: 1. Request detection
2. Request detection not established.
Figure 9.43 Timing of DREQ Pin Input Detection in Cycle Steal Mode
Requests can be detected for the first time 3 cycles after the bus cycle prior to the DMAC read
cycle and starts sometime between then and 2 cycles after DACK output (figure 9.43). This
varies with the fluctuations of waits and the like. This means that if request output is stopped
within 3 cycles from the bus cycle prior to the DMAC read cycle, the next DMA transfer is
not performed; if request output is stopped within 2 cycles of DACK output, the next DMA
transfer may sometimes be performed.
with Level Detection (3)
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