Hitachi SH7095 Hardware User Manual page 518

Break control register (BRCR)
Item 15
Bit name CMF CMF
CA PA EBBEUMD
Initial Value 0
R/W R/W R/W R/W R/W
Bit Bit Name
15 CPU condition-match
flag A (CMFCA)
14 Peripheral condition-
match flag A (CMFPA)
13 External bus break
enable (EBBE)
12 UBC mode (UMD)
10 PC break select A
(PCBA)
7 CPU condition-match
flag B (CMFCB)
6 Peripheral condition-
match flag B (CMFPB)
4 Sequence condition
select (SEQ)
3 Data break enable B
(DBEB)
2 Instruction break select
B (PCBB)
H'FFFFFF78
14 13 12 11
– PCBA –
0 0 0 0
R
Value
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
Bit
10 9 8 7
CMF CMF
– CB PB
0 0 0 0
R/W R R R/W R/W R
Channel A CPU cycle conditions do not match, no user
break interrupt generated
Channel A CPU cycle conditions have matched, user
break interrupt generated
Channel A peripheral cycle conditions do not match, no
user break interrupt generated
Channel A peripheral cycle conditions have matched,
user break interrupt generated
Chip-external bus cycle not included in break conditions
Chip-external bus cycle included in break conditions
Compatible mode for SH7000-series UBCs (initial value)
SH7095 mode
Places the channel A instruction fetch cycle break before
instruction execution
Places the channel A instruction fetch cycle break after
instruction execution
Channel B CPU cycle conditions do not match, no user
break interrupt generated
Channel B CPU cycle conditions have matched, user
break interrupt generated
Channel B peripheral cycle conditions do not match, no
user break interrupt generated
Channel B peripheral cycle conditions have matched,
user break interrupt generated
Compare channel A and B conditions independently
Compare channel A and B conditions sequentially
(channel A, then channel B)
Do not include data bus conditions in the channel B
conditions
Include data bus conditions in the channel B conditions
Places the channel B instruction fetch cycle break before
instruction execution
Places the channel B instruction fetch cycle break after
instruction execution
UBC
16/32
6 5 4 3
– SEQ DBEBPCBB –
0 0 0 0
R/W R/W R/W
Description
2 1 0
–
0 0 0
R R
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
Hitachi 507