Pseudo-Sram Interface; Pseudo-Sram Direct Connection - Hitachi SH7095 Hardware User Manual

7.7

Pseudo-SRAM Interface

7.7.1

Pseudo-SRAM Direct Connection

When the DRAM and other memory enable bits (DRAM2–DRAM0) of BCR1 are set to 011, CS3
space becomes pseudo-SRAM space, and the pseudo SRAM interface function can be used to
directly connect the SH7095 to a pseudo SRAM. The interface data width is 16 or 32 bits.
The refresh and output enable signals of the connected pseudo SRAM are multiplexed. The signals
used for connecting pseudo SRAM are the CE, OE, WE3, WE2, WE1, and WE0 signals. The
WE3 and WE2 signals are not used when the data width is 16 bits. When a non-multiplexed
pseudo SRAM is connected, the RD signal is also used.
In addition to ordinary read and write access, burst access using the static column access function
is also supported. Figure 7.36 shows an example of connections to a 1-M pseudo SRAM with
isolated OE and RFSH pins; figure 7.37 shows an example of connections to a 4-M pseudo SRAM
with multiplexed OE and RFSH pins. 256-k pseudo SRAM is multiplexed just like the 4-M
pseudo SRAM. All data widths are 32 bits.
178 Hitachi