Break Control Register (Brcr) - Hitachi SH7095 Hardware User Manual

6.2.9

Break Control Register (BRCR)

Bit:
Bit name: CMFCA CMFPA
Initial value:
R/W:
Bit:
Bit name: CMFCB CMFPB
Initial value:
R/W:
The BRCR:
1. Determines whether to use channels A and B as two independent channels or as sequential
conditions.
2. Selects SH7000 series compatible mode/SH7095 mode.
3. Selects whether to break before or after instruction execution during the instruction fetch
cycle.
4. Enables/disables external bus.
5. Determines whether to include data bus on channel B in comparison conditions.
It also has a condition-match flag that is set when conditions match. A power-on reset initializes
BRCR to H'0000.
• Bit 15—CPU condition-match flag A (CMFCA): Set to 1 when the conditions for CPU bus
cycle that are break conditions set in channel A are met. Not cleared to 0.
Bit 15: CMFCA
0
1
• Bit 14—Peripheral condition-match flag A (CMFPA): Set to 1 when the conditions for
peripheral bus cycle (external bus cycle when the on-chip DMAC or external bus monitor are
enabled) that are break conditions set in channel A are met. Not cleared to 0.
15 14
EBBE
0 0
R/W R/W R/W
7 6
0 0
R/W R/W
Description
Channel A CPU cycle conditions do not match, no user break interrupt
generated (initial value).
Channel A CPU cycle conditions have matched, user break interrupt
generated.
13 12 11
UMD —
0 0
R/W
5 4
— SEQ DBEB
0 0
R R/W
10
PCBA —
0 0
R R/W
3 2
RWAB —
0 0
R R/W
9 8
—
0 0
R R
1 0
—
0 0
R R
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