Hitachi SH7095 Hardware User Manual page 274

Transfer Width: 16-byte
Transfer bus mode: Cycle steal mode
Transfer address mode: Dual mode
DREQ detection method: Edge detection
DACK output timing: DMAC read and write cycle
Bus cycle: Basic bus cycle
Notes 1. Request detection
2. When a write (dual) occurs at DACK output, the cycle is a DMAC read out.
Otherwise, the cycle is a CPU cycle.
3. When a write (dual) occurs at DACK output, the cycle is a DMAC write. The cycle
is a DMAC read in when the read in (dual) occurs.
Figure 9.38 DREQ Pin Input Detection Timing in Cycle Steal Mode with Edge Detection (2)
Requests can be detected 2 cycles after DACK output. After that point, the request is input to
DREQ. (When input prior to that point, requests are sometimes detected by internal state,
sometimes not.) DACK is output synchronous to all 4 transfers (figure 9.38).
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