Hitachi SH7095 Hardware User Manual page 317

Figure 11.16 Contention between OCR and Compare Match
5. Internal Clock Switching and Counter Operation
The FRC will sometimes begin incrementing because of the timing of switching between
internal clocks. Table 11.4 shows the relationship between internal clock switching timing
(CKS1 and CKS0 bit rewrites) and FRC operation.
When an internal clock is used, the FRC clock is generated when the falling edge of an
internal clock (created by dividing the system clock (φ)) is detected. When a clock is switched
to high before the switching and to low after switching, as shown in number 3 of table 11.4,
the time of the switch is considered a falling edge and an FRC clock is generated, causing the
FRC to begin incrementing. The FRC will also start incrementing when switching between an
internal clock and an external clock.
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