Control Signal Timing - Hitachi SH7095 Hardware User Manual

15.3.2

Control Signal Timing

Table 15.5 Control Signal Timing (Conditions: V
Item
RES rise, fall
RES pulse width
NMI reset setup time
NMI reset hold time
NMI rise, fall
NMI minimum pulse width
*
RES setup time
*
NMI setup time
IRL3–IRL0 setup time
RES hold time
NMI hold time
IRL3–IRL0 hold time
BRLS setup time 1 (PLL on)
BRLS hold time 1 (PLL on)
BGR delay time 1 (PLL on)
BRLS setup time 1 (PLL on, 1/4 cycle delay) t
BRLS hold time 1 (PLL on, 1/4 cycle delay)
BGR delay time 1 (PLL on, 1/4 cycle delay)
BRLS setup time 2 (PLL off)
BRLS hold time 2 (PLL off)
BGR delay time 2 (PLL off)
Note The RES, NMI and /IRL3-/IRL0 signals are asynchronous inputs, but when the setup times
shown here are provided, the signals are considered to have produced changes at clock
fall. If the setup times are not provided, recognition is delayed until the next clock fall.
392 Hitachi
*
= 5.0 V ±10%, Ta = –20 to +75°C)
CC
Symbol Min
t , —
RESr
t
RESf
t 20
RESW
t tcyc + 10
NMIRS
t tcyc + 10
NMIRH
t , t —
NMIr NMIf
t 3
IRQES
t 30
RESS
t 30
NMIS
t 30
IRLS
t 10
RESH
t 10
NMIH
t 10
IRLH
t 1/2 tcyc + 9
BLSS1
t 9 – 1/2 tcyc
BLSH1
t —
BGRD1
1/4 tcyc + 9
BLSS1
t 9 – 1/4 tcyc
BLSH1
t —
BGRD1
t 9
BLSS2
t 19
BLSH2
t —
BGRD2
Max Unit
200 ns
— t
cyc
— ns
— ns
200 ns
— tcyc
— ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns
1/2 tcyc+18 ns
— ns
— ns
3/4 tcyc + 18 ns
— ns
— ns
28 ns
Figure
15.7
15.8,
15.9
15.8,
15.9
15.10
15.10
15.11