Hitachi SH7095 Hardware User Manual page 112

• Bits 7 and 6—CPU Cycle/Peripheral Cycle Select A (CPA1, CPA0): These bits select
whether to break channel A on a CPU and/or peripheral bus cycle. Peripheral cycles are
conditioned upon on-chip DMACs or when the bus released on the bus cycles of external bus
masters. When set for peripheral cycle, the on-chip DMAC cycle always includes a break
condition; the external bus master cycle, however, allows selection for whether the condition
set with the EBBE bit of the BRCR register set is included.
Bit 7: CPA1 Bit 6: CPA0
0 0
1
1 0
1
• Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): These bits select
whether to break channel A on instruction fetch and/or data access cycles.
Bit 5: IDA1 Bit 4: IDA0
0 0
1
1 0
1
• Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits select whether to break
channel A on read and/or write cycles.
Bit 3: RWA1 Bit 2: RWA0
0 0
1
1 0
1
• Bits 1 and 0—Operand Size Select A (SZA1, SZA0): These bits select bus cycle operand size
as a channel A break condition.
Description
No channel A user break interrupt occurs (initial value)
Break only on CPU cycles
Break only on peripheral cycles
Break on both CPU and peripheral cycles
Description
No channel A user break interrupt occurs (initial value)
Break only on instruction fetch cycles
Break only on data access cycles
Break on both instruction fetch and data access cycles
Description
No channel A user break interrupt occurs (initial value)
Break only on read cycles
Break only on write cycles
Break on both read and write cycles
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